Multi state sensing of NAND memory cells by varying source bias

ABSTRACT

A method and circuit for sensing multi states of a NAND memory cell by varying source bias, at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the source bias, and sensing the memory cell state.

FIELD OF THE INVENTION

The present invention relates to NAND memory cells used in non-volatileflash memory architecture. More specifically, it relates to sensingmulti-levels in a NAND memory cell by applying a source bias voltage.

BACKGROUND OF THE INVENTION

A conventional NAND EEPROM (Electrically erasable programmable read onlymemory) array block is formed by a series of floating gate transistorscoupled in series between a select drain transistor and a select sourcetransistor. The select drain transistor is coupled to a data transferline called bit line (BL) and the select source transistor is coupled toa source line. Each floating gate transistor is a memory cell having afloating gate which is programmed and erased using techniques well knownto one skilled in the art. The memory cell transistors are floating gateMOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

Conventionally, prior to programming the floating gate of a memory cellis biased to a negative voltage relative to the substrate by storingelectrons into the floating gate. A floating gate of a memory cell isthen programmed by turning the select source and drain transistors offto isolate the series of memory cells, biasing a control gate at theprogramming voltage, and grounding the body region. The substrate isbiased, while the control gate is grounded, thereby driving theelectrons from the floating gate back into the substrate.

Each NAND memory cell can be programmed into one of several states whichcan be designated, for example as follows:

(0,0) denotes an erased state;

(0,1) denotes a partially erased state;

(1,0) denotes a partially programmed state; and

(1,1) denotes a programmed state.

Currently, several reference voltages (Vref1, Vref2 and Vref3) areapplied to NAND memory cells for sensing the state of a memory cell. Thereference voltage and the state of the memory cell determine a cellcurrent in a sensing circuit. For example a memory cell is conductivewhen erased, and hence pulls down the sense node. If the memory cell isprogrammed then it is not conductive and the sense node is pulled up.The state of the memory cell can be determined by analyzing thevariation in the current in the sensing circuit caused by applying areference voltage. “A Non-Volatile semiconductor memory device forstoring multivalue data and readout/write-in method” is disclosed inU.S. Pat. No. 5,751,634. (Itoh). Similar to the method described above,in Itoh, reference voltages are applied at individual memory cellsduring data writing and data readout time, generating memory cellcurrent in response to the reference voltages. The variation in memorycell currents provide the state of the memory cell. The disadvantage ofItoh is that when high reference voltages are applied to a memory cell,the reference voltage may cause disturbance in memory cells adjacent tothe memory cell that is sensed at a given time.

Another method to sense the state of a NAND memory cell is by applyingan external bias current at 0v and evaluating a cell current generatedin response to the external bias current. The disadvantage of such amethod is that only two states (0,0) and (1,1) can be sensed.

Therefore, what is desired is a circuit and a method that efficientlysenses the levels of a multi state NAND memory cell without causingsignificant disturbance to memory cells adjacent to the memory cellsensed at any given time.

SUMMARY OF THE INVENTION

The present invention is a method and circuit for sensing the state of amulti-state NAND memory cell in a NAND string connected to a bit line bydefining plural NAND memory cell states, applying a source bias voltageat the source terminal, at zero gate voltage and detecting a cellcurrent in response to the applied source bias voltage. Finally, sensingthe NAND memory cell state by measuring the cell current in response tothe source bias voltage. The source bias generates reverse and forwardvoltage.

The present invention has the advantage of sensing plural states of NANDmemory cells at zero gate voltage and hence minimizes any disturbancedue to various reference voltages applied to NAND memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional diagram of a floating type memory cell.

FIG. 2 is a schematic diagram of a NAND array block.

FIG. 3 is a cross sectional diagram of the string of FIG. 2 as disposedon a substrate.

FIG. 4a is a diagram showing four states of a NAND memory cell.

FIGS. 4b and 4 c are the I-V characteristic of a NAND memory cell atzero gate voltage.

FIG. 5 shows a NAND cell sensing circuit of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a cross-sectional diagram of a floating gate memory cell 100of a NAND array block. Memory cell 100 is a floating gate transistorhaving a control gate 102 coupled to a voltage line 122 for applying avoltage of V_(g). on control gate 102. Control gate 102 is separatedfrom a floating gate 106 by an upper insulating layer 104, the floatinggate 106 being separated from a substrate 110 by a lower insulatinglayer 108.

Substrate 110 includes an n+ source region 112 coupled to a voltage line132 for applying a voltage of V_(s) on n+ source region 112, a p-dopedbody region 114 coupled to a voltage line 134 for inducing a voltage onp-doped body region 114, and an n+ drain region 116 coupled to a voltageline 136 for applying a voltage of V_(D) on n+ drain region 116.

FIG. 2 is a schematic diagram of a conventional NAND array block 200.Block 200 includes an external bit line BL coupled to a sense circuit220 for detecting a voltage change on external bit line BL. Select draintransistor SG1 couples bit line BL to string 210 while string 210includes select drain transistor SG1 and internal bit line IBL coupledin series between external bit line BL and a source line 240.

Internal bit line IBL connects a NAND structure of 16 floating gatememory cells MC1 to MC16 connected in series between select gatetransistors SG1 and SG2.(for clarity reasons, only memory cells MC1 toMC3 and MC15 to MC16 are shown in FIG. 2). Other configurations of 4, 16or 32 memory cells may also be used. Memory cell MC3 can be implementedby memory cell 100 of FIG. 1. One terminal of memory cell MC16 in thestring 210 is coupled to select source transistor SG2 that is connectedto source line 240.

Each control gate of memory cells MC1 to MC16, WL1 to WL16 is coupled toa pass transistor (one of transistors T1 to T16) while the control gateof select drain transistor SD is coupled by transistor TO to selectdrain line SDL. Each of transistors To to T17 is coupled to charge pump230 by pump line PL for applying voltages on lines SDL and WL1 to WL16to the respective control gates of select drain transistor SG1 and SG2,and memory cells MC1 to MC16.

FIG. 3 is a cross sectional diagram of string 200 of FIG. 2 as disposedon a substrate 300. Memory cells MC1 to MC16, of which, for clarityreasons, only memory cells MC1 to MC4 and MC14 to MC16 are shown in FIG.3, are fabricated on a substrate 300.

Substrate 300 includes a p-well region 302, which is a body region formemory cells MC1 to MC16. P-well region 302 is coupled to voltage line134 for asserting voltage V_(pw) on p-well region 302. Substrate 300also has n+ regions 304 which form n+ source and drain regions of memorycells MC1 to MC16.

FIG. 4a is a graphical representation of the four states of a memorycell as a function of Id (cell current) and gate voltage V_(g) where thesource voltage V_(s) and the P well back bias (V_(pw))is zero andexternal bias on the bit line BL is constant.

FIG. 5 is a circuit diagram that senses multi levels of NAND memorycells according to the present invention. The circuit includes a sensenode 501, that senses variations in NAND memory cell current, aflip-flop latch 502 with gates 503 and 504 preconditioned to states 0and 1, and a pulse source 505 generates reverse and forward biasvoltage. For illustration purposes memory cell MC3 is sensed at a giventime t.

A fixed gate voltage (V_(g)) of 0V is applied to cell MC3 at time t.V_(pw) is at zero volts and voltage on external bit line BL is keptconstant. V_(s) is varied and that varies the memory cell current Id,depending upon memory cell MC3's state. If memory cell MC3 is in anerased state, it is conductive and if memory cell MC3 is programmed,then it is not conductive.

FIG. 4b shows the I-V characteristic of memory cell MC3 when a negativeV_(s) is applied at zero gate voltage, zero V_(pw) and a fixed externalbit line voltage. V_(s) causes a shift of the IV characteristics in thepositive direction along the voltage axis and thus differentiatesbetween states (0,0), (0,1) and states (1,0) (1,1), since a current Idonly flows in states (0,0) and (0,1) at zero gate voltage. FIG. 4c showsthe I-V characteristic of memory cell MC3 when a positive V_(s) isapplied at zero gate voltage, zero V_(pw) and fixed external bit linebias voltage. In this case, V_(s) causes a further shift of the I-Vcharacteristic curves in the positive direction along the voltage axisand differentiates between states (0,0) and (0,1) since current Id flowsonly in state (0,0). Hence the four states of memory cell MC3 aredifferentiated and sensed by applying plural V_(s).

Memory cell MC3 generates a cell current as a result of its memory cellstate and the value of V_(s). If memory cell MC3 is conductive, it is inan erased state and pulls down sense node 501. The flip-flop latchcircuit 502 stays in the same condition (0,1). If memory cell MC3 isprogrammed, it does not conduct and pulls up sense node 501, generatinga signal that flips the flip-flop 502 to a 1,0 state. An output signalIo1 from the flip-flop 502 circuit is sent to a logic circuit (notshown). The output signal will vary with the cell current Id that varieswith applied V_(s) and the state of memory cell MC3.

Based upon the output signals from the flip-flop circuit, particularmemory cell state is determined. The process is repeated atpre-determined intervals for every memory cell in the NAND array.

Although the present invention has been described with reference tospecific embodiments, these embodiments are illustrative only and notlimiting. Many other applications and embodiments of the presentinvention will be apparent in light of this disclosure and the followingclaims.

What is claimed is:
 1. A method for sensing the state of a multi stateof a NAND memory cell in a NAND array connected to a bit line,comprising the steps of: applying a source bias at the memory cell at aconstant gate voltage; detecting a memory cell current, in response tothe source bias voltage; and determining the NAND memory cell statecorresponding to the memory cell current.
 2. The method of claim 1further comprising: sending a signal in response to the memory cellcurrent to a latch circuit with a sense node connected to the NANDarray.
 3. The method of claim 1, wherein the constant gate voltage iszero volts.
 4. A circuit for sensing multi states of a NAND memory cellcomprising of: a NAND string of memory cells connected to an externalbit line, wherein the memory cells are connected in series; a source forvarying a source bias at a memory cell at a constant gate voltage of 0v;a sense node for sensing a memory cell current in response to the sourcebias; and a latch circuit to flip from a pre-conditioned state basedupon a signal generated in response to the memory cell current.